Thyristor Memory Cell with Assist Device

ABSTRACT

A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is a continuation of U.S. patent applicationSer. No. 15/349,978, filed Nov. 11, 2016, issued as U.S. patent Ser. No.10/020,308 on Jul. 10, 2018, which claims the benefit of U.S. patentapplication 62/345,203, filed Jun. 3, 2016 and is a continuation-in-partof U.S. patent application Ser. No. 15/197,640, filed Jun. 29, 2016,which are incorporated by reference along with all other referencescited in this application.

BACKGROUND OF THE INVENTION

This invention is related to integrated circuit devices and, inparticular, to semiconductor-based memory, such as static random accessmemory (SRAM) and dynamic random access memory (DRAM).

A DRAM is a type of random-access memory that stores a bit of data in acapacitor coupled to a transistor within the integrated circuit.Lithographic scaling and process enhancement may quadruple the number ofbits of storage in a DRAM approximately every three years. However, theindividual memory cells have become so small that maintaining thecapacitance of each cell while reducing charge leakage may significantlylimit further reductions in size.

What is needed is a memory unit cell that is smaller than theconventional one-capacitor one-transistor cell, that is readily scalablebelow 20 nm design rules, that is compatible with standard bulk siliconprocessing, and that consumes less power, both statically anddynamically.

BRIEF SUMMARY OF THE INVENTION

This invention provides a memory array suitable in which vertical PNPNthyristors are formed in bulk silicon substrate and isolated from eachother by a shallow trench of insulating material in one direction and adeeper trench of insulating material in a perpendicular direction. Thearray of memory cells is arranged in a cross-point grid andinterconnected by metal conductors and buried heavily doped layers.

In an embodiment of the present claimed invention, the memory arrayincludes row lines and column lines with anode of thyristor connected torow line, such as bit line, and cathode of thyristor coupled to columnline, such as word line. The substrate may be P-conductivity type withN-conductivity type buried layer extending in a first direction toprovide a column line. Alternating P-conductivity type andN-conductivity type layers over the buried layer provide the bases ofthe thyristor, with an upper P-conductivity type layer providing theanode of the thyristor. A conductive layer coupled to the anode of thethyristor extends in a second direction orthogonal to the firstdirection to provide a row line.

A gate line may be formed in the trench to provide NMOS or PMOStransistors to assist write speed of adjacent thyristor memory cell.

In an embodiment, the gate line may be parallel to a bit line.

In an embodiment, the gate line may be parallel to a word line.

In an embodiment, the gate line may include an NMOS transistor.

In an embodiment, the gate line may include a PMOS transistor.

In an embodiment, the gate line may be shared by two adjacent thyristormemory cells.

In an embodiment, the gate line may be self-aligned.

In an embodiment, the gate line may be located nearer to one adjacentthyristor memory cell and located farther from the other adjacentthyristor memory cell.

Other objects, features, and advantages of the present invention willbecome apparent upon consideration of the following detailed descriptionand the accompanying drawings, in which like reference designationsrepresent like features throughout the figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plane view of a layout of a 2×2 vertical thyristor memorycell array as implemented in an integrated circuit according to anembodiment of a claimed invention.

FIG. 2A illustrates a perspective view of perpendicular cross-sectionsof a vertical thyristor memory cell with a PMOS assist gate parallel toword line according to an embodiment of a claimed invention.

FIG. 2B illustrates a perspective view of perpendicular cross-sectionsof a thyristor memory cell with an NMOS assist gate parallel to wordline according to an embodiment of a claimed invention.

FIG. 3A illustrates a perspective view of perpendicular cross-sectionsof a vertical thyristor memory cell with a PMOS assist gate parallel tobit line according to an embodiment of a claimed invention.

FIG. 3B illustrates a perspective view of perpendicular cross-sectionsof a vertical thyristor memory cell with an NMOS assist gate parallel tobit line according to an embodiment of a claimed invention.

FIG. 4 illustrates doping profile of a vertical thyristor according toan embodiment of a claimed invention.

FIG. 5 illustrates cross-section of vertical thyristor with NMOS assistgate located below upper edge and above lower edge of p-base accordingto an embodiment of a claimed invention.

FIG. 6A illustrates a perspective view of perpendicular cross-sectionsof a vertical thyristor memory cell with a PMOS assist gate completelyaround the vertical thyristor according to an embodiment of a claimedinvention.

FIG. 6B illustrates a perspective view of perpendicular cross-sectionsof a thyristor memory cell with an NMOS assist gate partially around thevertical thyristor according to an embodiment of a claimed invention.

DETAILED DESCRIPTION OF THE INVENTION

This invention discloses position of an assist gate relative to an upperedge and a lower edge of a base of a vertical thyristor memory cell inan array.

FIG. 1 shows a plane view of a layout of a 2×2 vertical thyristor memorycell array as implemented in an integrated circuit according to anembodiment of a claimed invention.

The four vertical thyristors, including anodes, are located at thecorners of the layout. The thyristors are separated in two perpendiculardirections with trenches filled with oxide.

A first set of parallel conductive lines provides a word line for eachrow of the memory array by being coupled to the cathodes of thethyristors in the row. A second set of parallel conductive linesprovides a bit line for each column of the memory array by being coupledto the anodes of the thyristors in the column. The word lines areperpendicular to the bit lines.

FIG. 4 shows doping profile of a vertical thyristor according to anembodiment of a claimed invention. The doping concentration varies as afunction of depth below the upper surface. In an embodiment of thepresent claimed invention, some peaks may include a shoulder (notshown). The dose may have a tolerance of +/−6% while the ionimplantation energy may have a tolerance of +/−2%.

In an embodiment, an assist device, such as a gate, such as PMOS orNMOS, may be formed next to the sidewalls of the isolation trenchesadjacent the thyristor. The assist gates may increase write speed andmay reduce write voltage.

The sidewalls of the trench are oxidized, thus forming the gate oxidethat isolates the gate electrodes from the doped regions. In anembodiment of the present claimed invention, the gate oxide may have athickness of 3.0 (+/−0.3) nm.

The trenches are then partially filled with silicon dioxide, such as bya chemical vapor deposition process.

Then a conformal doped-polycrystalline silicon layer is deposited overthe structure.

An anisotropic etching step removes the entire conformal polycrystallinesilicon layer except for a desired thickness to form a gate (control)line that includes the assist gate.

Then, another trench filling operation is performed to finish fillingthe trenches.

Planarization steps are then performed, such as by using chemicalmechanical polishing or other techniques.

Later, an electrical connection is made to couple the gate (control)lines.

As shown in FIG. 2(a), a PMOS assist gate 80 may be positioned adjacentto the n-base of the vertical thyristor. The PMOS assist gate 80 may runparallel to the word lines (WL) and orthogonal to the bit lines (BL).The word lines may be buried and connected with a conductor in (andthrough) the isolation trench.

As shown in FIG. 2 (b), an NMOS assist gate 86 may be positionedadjacent to the p-base of the vertical thyristor. The PMOS assist gate86 may run parallel to the word lines. The word lines may be buried andconnected with a conductor in (and through) the isolation trench.

As shown in FIG. 3(a), a PMOS assist gate 80 may be positioned adjacentto the n-base of the vertical thyristor. The PMOS assist gate 80 may runparallel to the bit lines. The bit lines may include an overlying M1.

As shown in FIG. 3(b), an NMOS assist gate 86 may be positioned adjacentto the p-base of the vertical thyristor. The PMOS assist gate 86 may runparallel to the bit lines. The bit lines may include an overlying M1.

In an embodiment of the present claimed invention, the p-base may have aheight of 110.0 (+/−11.0) nm.

In an embodiment of the present claimed invention, the NMOS assist gatemay have a gate length (vertical height) of 55.0 (+/−5.5) nm.

As shown in an embodiment of the present claimed invention in FIG. 5, anupper edge of the NMOS assist gate (G) may be positioned about 30.5(+/−3.0) nm below an upper edge of the p-base sPW which in turnunderlies sNW.

As shown in an embodiment of the present claimed invention in FIG. 5, alower edge of the NMOS assist gate may be positioned about 24.5 (+/−2.5)nm above a lower edge of the p-base which in turn overlies bNW.

In other embodiments, the assist gates may be formed—partially, inseparate segments, or completely—around the vertical thyristor, such asillustrated by FIGS. 6(a) and 6(b).

In other embodiments, the sidewall gates 80, 86 may be formed from otherconductive material, such as metal, such as tungsten, or silicide(s), orcombinations of different materials.

In an embodiment of the present claimed invention, p+ anodes areconnected to bit lines (M1 layer) while n+ anodes are connected to wordlines (M2 layer straps between drops for about every 32 verticalthyristors) are connected to N+ cathodes.

This description of the invention has been presented for the purposes ofillustration and description. It is not intended to be exhaustive or tolimit the invention to the precise form described, and manymodifications and variations are possible in light of the teachingabove. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical applications.This description will enable others skilled in the art to best utilizeand practice the invention in various embodiments and with variousmodifications as are suited to a particular use. The scope of theinvention is defined by the following claims.

The invention claimed is:
 1. A vertical thyristor memory arraycomprising: a vertical thyristor memory cell, the vertical thyristormemory cell comprising: a p+ anode; an n-base disposed below the p+anode; a p-base disposed below the n-base; a n+ cathode disposed belowthe p-base; an isolation trench disposed around the vertical thyristormemory cell; an assist gate disposed in the isolation trench adjacentthe n-base wherein an entire vertical height of the assist gate isdisposed within an entire vertical height of the n-base.
 2. The verticalthyristor memory array of claim 1 wherein the assist gate comprisesP-type coupling capacitor.
 3. The vertical thyristor memory array ofclaim 1 wherein the assist gate runs orthogonal to the anode lines. 4.The vertical thyristor memory array of claim 1 wherein the assist gateruns parallel to the anode lines.
 5. A vertical thyristor memory arraycomprising: A vertical thyristor memory cell, the vertical thyristormemory cell comprising: a p+ anode; an n-base disposed below the p+anode; a p-base disposed below the n-base; a n+ cathode disposed belowthe p-base; an isolation trench disposed around the vertical thyristormemory cell; an assist gate disposed in the isolation trench adjacentthe p-base wherein an entire vertical height of the assist gate isdisposed within an entire vertical height of the p-base.
 6. The verticalthyristor memory array of claim 3 wherein the assist gate comprisesNMOS.
 7. The vertical thyristor memory array of claim 1 wherein theassist gate runs parallel to the anode lines.
 8. The vertical thyristormemory array of claim 1 wherein the assist gate runs parallel to theanode lines.